1. Technical Field
This disclosure generally relates to data error check, and more particularly to a data error check circuit, a data error check method, a data transmission method using a data error check function, a semiconductor memory apparatus and a memory system using the data error check function.
2. Related Art
A typical semiconductor circuit may have an error check function for checking whether an error has occurred in data in order to improve data reliability in high speed data transmission One typical error check method is a cyclic redundancy check (CRC) function.
FIG. 1 is a drawing depicting a typical semiconductor circuit having a conventional CRC function, where data transmission is performed through respective data input/output terminals DQ0 to DQ7 at ten unit intervals (UI).
In the ten unit intervals, 8-bit data is assigned to eight unit intervals (or expressed by BL8 (Burst Length=8)), a 1-bit CRC values (CRC—0 to CRC—7) is assigned to a ninth unit interval next to the eight unit intervals, and a tenth unit interval actually not used is assigned. The tenth unit interval may be fixed to a logic high value ‘1’.
The CRC logic of this typical semiconductor circuit according to the conventional art, for example, has to be expressed in a polynomial form such as P(x)=x^8+x^5+x^3+x^2+x+1 in order to detect a multi-bit error such as a single bit error, a double bit error or a triple bit error.
In order to configure the CRC logic, the total 328 2-input XOR gates and 42 polynomial equations are necessary, resulting in an increase in a circuit area.
Furthermore, final CRC values are calculated by passing through a 6-stage XOR gate path, causing 6-stage gate delay.
One problem with typical semiconductor circuits according to the conventional art is that circuit area and error check time are increased due to the equations mandated by the CRC logic.